This invention relates to integrated circuit memory devices and more particularly to redundancy circuits for integrated circuit memory devices.
As the integration density of integrated circuit memory devices increases, redundancy systems may be used to increase device yields. In general, redundancy systems provide spare rows and/or spare columns of memory cells, and redundancy circuits for activating a spare row and/or column of memory cells. Accordingly, when an address signal specifying a memory cell of a defective row or a defective column is input, a spare row or column memory cell, rather than a normal memory cell, is selected by the input address. Redundancy systems are described, for example, in U.S. Pat. Nos. 5,742,547 to Lee, entitledxe2x80x9cCircuits for Block Redundancy Repair of Integrated Circuit Memory Devices;xe2x80x9d 5,761,138 to Lee et al., entitled xe2x80x9cMemory Devices Having A Flexible Redundant Block Architecturexe2x80x9d and 5,777,931 to Kwon et al., entitled xe2x80x9cSynchronized Redundancy Decoding Systems and Methods for Integrated Circuit Memory Devices,xe2x80x9d all of which are assigned to the assignee of the present application, the disclosures of all of which are hereby incorporated herein by reference.
FIG. 1 is a block diagram of a conventional redundancy circuit. Referring to FIG. 1, a plurality of unit redundancy circuits 11131, 11132, 11133, . . . control the respective redundant memory cell arrays. The unit redundancy circuits 11131, 11132, 11133, . . . are enabled by a power-up signal PWUP that is activated when power is supplied to the integrated circuit memory device and activate redundant signals REDL1, REDL2, REDL3, . . . for selecting addresses and the cells of the corresponding redundant memory cell arrays. A power supply voltage VCC is supplied to the respective redundancy circuits.
FIG. 2 shows an embodiment of a unit redundancy circuit of FIG. 1. Referring to FIG. 2, a drain terminal N24 of an NMOS transistor 23 becomes a low level by turning on the NMOS transistor 23 in response to the power-up signal PWUP which is a pulse signal activated to a high level when the power is supplied to the integrated circuit memory device. The drain node N24 of the NMOS transistor 23 is inverted by an inverter 27.
A conventional redundancy circuit as shown in FIG. 2 includes a plurality of transfer means 29131, 29132, . . . for transferring address signals A0, A1, . . . and inverted address signals /A0, /A1, . . . . The transfer means 29131, 29132, . . . may be embodied as transfer gates in order to transfer address signals and inverted address signals without undue delay. A transfer gate generally includes at least one NMOS transistor (Ni, i=1, 2, . . .) and one PMOS transistor (Pi, i=1, 2, . . .). The PMOS transistor Pi is gated by a signal from the drain node N24 of the NMOS transistor 23. The NMOS transistor Ni is gated by the output node N28 of the inverter 27.
Unfortunately, the transfer means 29131, 29132, . . . realized by the PMOS transistor and the NMOS transistor of FIG. 2 may increase the layout area of the redundancy circuits in the integrated circuit memory device. Specifically, as the size of the memory device increases, the number of address signals also may increase. If the number of addresses for selecting the redundant memory cell of the redundant memory cell array is j, 4j MOS transistors may be used for transferring j address signals and j inverted address signals. Therefore, the MOS transistors and buses for gating the MOS transistors may increase in FIG. 2, thus increasing the layout area of the redundancy circuits in the integrated circuit memory device.
It is also known to provide redundancy circuits that do not require the use of transfer gates. See, for example, the above cited U.S. Pat. No. 5,777,931. Notwithstanding these advances, there continues to be a need for improved integrated circuit memory device redundancy circuits.
The present invention provides integrated circuit memory device redundancy circuits that include a plurality of field effect transistors and fuses, respective field effect transistor and a respective fuse being serially coupled between a respective address line and a logic circuit to generate a selection signal for a redundant memory cell in response to a predetermined address on the address lines. A pump-up circuit generates a pump-up voltage from a power supply voltage, wherein the pump-up voltage is greater than the power supply voltage. The pump-up voltage is applied to the gates of the field effect transistors to activate the redundancy circuit. Complementary transfer gates therefore are not needed, and the layout of the integrated circuit may be reduced.
The redundancy circuits preferably also include a plurality of second field effect transistors, wherein a respective (first) field effect transistor, a respective fuse and a respective second field effect transistor are serially coupled between a respective address line and ground voltage. The pump-up voltage is applied to the gates of the second plurality of field effect transistors to deactivate the redundancy circuit. An inverter may also be provided that is powered by the pump-up voltage. The inverter output is coupled to the gates of the first field effect transistors and the inverter input is coupled to the gates of the second field effect transistors.
An enable controlling circuit also may be provided that is coupled to the inverter input and that is responsive to a repair control signal. The enable controlling circuit preferably comprises a first fuse, a field effect transistor and a second fuse that are serially coupled between the pump-up voltage and ground voltage. The gate of the third field effect transistor is coupled to the repair control signal.
According to another aspect of the present invention, a redundancy circuit for an integrated circuit memory device comprises a repair controlling circuit that includes a repair fuse and that generates a repair control signal in response to opening of the repair fuse. The enable controlling circuit is responsive to the repair controlling circuit and includes an enable fuse to generate a redundant enable signal in response to the repair control signal and opening of the enable fuse. A redundancy signal generator is responsive to the enable controlling circuit to generate a selection signal for a redundant memory cell in response to receipt of an address of a defective memory cell.
More specifically, the enable controlling circuit includes the enable fuse, a field effect transistor and a stabilizing fuse that are serially coupled between first and second reference voltages. The repair control signal is coupled to the gate of the field effect transistor. The enable fuse and the field effect transistor define a node therebetween that is coupled to the redundancy signal generator, such that the redundancy signal generator is deactivated by the enable controlling circuit in response to opening of the stabilizing fuse. The redundancy signal generator preferably comprises the field effect transistors, fuses and pump-up circuit as described above. Accordingly, improved redundancy circuits may be provided.